The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to dry etching techniques of a metal gate electrode.
A silicon oxide film-based film such as a SiO2 film and a SiON film has been used for a long time as a gate insulation film of a semiconductor element. However, from requests of micro-processing rate of patterns and speeding up of an operation speed of semiconductor devices, thinning of a gate insulation film progresses and these gate insulation films reach the limit of thinning in recent years. To cope with the above-described problem, high dielectric such as HfSiO and HfO2, which can reduce a thickness of SiO2 gate oxide film having the same thickness to one part in several in terms of an equivalent gate insulation film thickness, is being used as alternate materials.
However, there occurs a problem that when the above-described high dielectric films are simply used as a gate insulation film in place of a previous gate oxide film, transistor characteristics are lowered, due to depletion of a polysilicon film, in an interface between the gate insulation film and polysilicon film of the gate electrode. However, this phenomenon is avoidable by sandwiching a metallic layer between the high dielectric gate oxide film and the polysilicon film, and the above-described metal/high dielectric gate structure is actually adopted as a gate structure for the next generation. A known example related to the technique includes, for example, JP-T-2008-502141 (the term “JP-T” as used herein means a published Japanese translation of a PCT application) (corresponding to U.S. Pat. No. 7,163,880).
For purpose of generally etching a metallic material, a gas (hereinafter, referred to as a halogen gas) composed of a halogen simple substance or halides is used. Further, since reaction products generated between the above-described etching gases and the metallic material have low volatility, the etching is hard to progress. Therefore, for processing a metallic material, the etching is required to be allowed to progress while improving volatility of the reaction product due to the rise in a wafer temperature or the low pressure of a processing pressure.
Further, JP-A-2007-250940 (corresponding to U.S. Patent Publication No. 2007/218696) discloses a technology for suppressing a side-etching shape generated by the etching processing, using reaction products generated by an addition gas (hydrocarbon), after main etching of the polysilicon film.